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| TECHNICAL DATA Synchronous 4 Bit Counters; Binary, Direct Reset This synchronous, presettable counter features an internal carry lookahead for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change conicident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input wave form. This counter is fully programmable; that is the outputs may be preset to either level. As presetting is synchronous setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. The carry look-ahead circuitry provides for cascading counters for nbit synchronous applications without additional gating. Instrumental in accomplishiing this function are two counter-enable inputs and a ripple carry output. Both countenable inputs (ENABLE P and ENABLE T) must be high to count, and ENABLE T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high level portion of the QA output. The high-level overflow ripple carry pulse can be enable successive cascaded stages. Transitions at the ENPor ENT are allowed regardless of the level of the clock input. * * * * * * Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Synchronous Counting Synchronously Programmable Load Control Line Diode-Clamped Inputs KK74LS161 ORDERING INFORMATION KK74LS161N Plastic KK74LS161D SOIC TA = 0 to 70 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM PIN 16 =VCC PIN 8 = GND 1 KK74LS161 FUNCTION TABLE Inputs Reset L H H H H H Load X L H H H X Enable P X X X L H X Enable T X X L X H X Clock X Q0 L P0 Outputs Q1 L P1 Q2 L P2 Q3 L P3 Function Reset to "0" Preset Data No count No count Count No count No change No change Count up No change X=don't care P0,P1,P2,P3 = logic level of Data inputs Ripple Carry Out = Enable T * Q0 * Q1 * Q2 * Q3 MAXIMUM RATINGS* Symbol VCC VIN VOUT Tstg * Parameter Supply Voltage Input Voltage Output Voltage Storage Temperature Range Value 7.0 7.0 5.5 -65 to +150 Unit V V V C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. RECOMMENDED OPERATING CONDITIONS Symbol VCC VIH VIL IOH IOL fclock tw(clock) tw(reset) tsu th TA Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Clock frequency Width of clock pulse Width of reset pulse Data inputs P0, P1, P2, P3 Setup time Hold time at any input Ambient Temperature Range Enable P or T Load 0 25 20 20 20 20 3 0 +70 ns C ns Parameter Min 4.75 2.0 0.8 -0.4 8.0 25 Max 5.25 Unit V V V mA mA MHz ns ns 2 KK74LS161 DC ELECTRICAL CHARACTERISTICS over full operating conditions Guaranteed Limit Symbol VIK VOH VOL IIH Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage High Level Input Current Test Conditions VCC = min, IIN = -18 mA VCC = min, IOH = -0.4 mA VCC = min, IOL = 4 mA VCC = min, IOL = 8 mA VCC = max VIN =2.7 V Data or enable P Load, clock or enable T Reset VCC = max VIN =7.0 V Data or enable P Load, clock or enable T Reset IIL Low Level Input Current VCC = max VIN =0.4 V Data or enable P Load, clock or enable T Reset -20 2.7 0.4 0.5 20 40 20 0.1 0.2 0.1 -0.4 -0.8 mA mA A Min Max -1.5 Unit V V V IO ICC Output Short Circuit Current Supply Current All outputs high All outputs low VCC = max, VO = 0 V (Note 1) VCC = max (Note 2) VCC = max (Note 3) -100 31 32 mA mA Note 1: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 2: ICCH is measured with the load high, then again with the load low, with all other inputs high and all outputs open. Note 3: ICCL is measured with the clock input high, then again with the clock input low, with all other inputs low and all outputs open. 3 KK74LS161 AC ELECTRICAL CHARACTERISTICS (TA=25C, VCC = 5.0 V, CL = 15 pF, RL = 2 k, tr =15 ns, tf = 6.0 ns) Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL Parameter Propagation Delay, Clock to Ripple carry Propagation Delay, Clock to Ripple carry Propagation Delay, Clock (load input high) to Any Q Propagation Delay, Clock (load input high) to Any Q Propagation Delay, Clock (load input low) to Any Q Propagation Delay, Clock (load input low) to Any Q Propagation Delay, Enable T to Ripple carry Propagation Delay, Enable T to Ripple carry Propagation Delay, Reset to Any Q Min Max 35 35 24 27 24 27 14 14 28 Unit ns ns ns ns ns ns ns ns ns Figure 1. Switching Waveform Figure 2. Switching Waveform Figure 3. Switching Waveform Figure 4. Switching Waveform 4 KK74LS161 NOTES A. CL includes probe and jig capacitance. B. All diodes are 1N916 or 1N3064. Figure 5. Test Circuit Sequence illustrated in waveforms: 1. Reset outputs to zero. 2. Preset to binary twelve. 3. Count to thirteen, fourteen, fifteen, zero, one, and two. 4. Inhibit. Figure 7. Timing Diagram 5 KK74LS161 N SUFFIX PLASTIC DIP (MS - 001BB) A Dimension, mm 16 9 B Symbol A MIN 18.67 6.1 MAX 19.69 7.11 5.33 1 8 B C F L D F 0.36 1.14 2.54 7.62 0 2.92 7.62 0.2 0.38 0.56 1.78 C -T- SEATING PLANE G H H J N G D 0.25 (0.010) M T K M J K L M N 10 3.81 8.26 0.36 NOTES: 1. Dimensions "A", "B" do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. D SUFFIX SOIC (MS - 012AC) Dimension, mm A 16 9 Symbol A MIN 9.8 3.8 1.35 0.33 0.4 1.27 5.72 0 0.1 0.19 5.8 0.25 MAX 10 4 1.75 0.51 1.27 H B P B C 1 G 8 C R x 45 D F G -TD 0.25 (0.010) M T C M K SEATING PLANE J F M H J K M P R 8 0.25 0.25 6.2 0.5 NOTES: 1. Dimensions A and B do not include mold flash or protrusion. 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B 0.25 mm (0.010) per side. 6 |
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